1) _________ is defined as the time required to process a single instruction.

1. ALU operation
2. Memory access
3. Throughput
4. Latency

2) Which of the followings is not an example of super-scalar processors

1. DEC Alpha 21164
2. Intel P6
3. IAPX88
4. Power 601

3) The third stage of the Pipelined version of SRC is:

1. ALU operation
2. Instruction Fetch
3. Memory access
4. Register writes

4) Which one of the following control signals causes the data from the bus to be read into the register MAR>

1. LMAR
2. MARout
3. None of the given
4. MARin

5) In structural RTL, the first three-time steps (i.e., T0. T1, T2) are of the instruction ___________ phase.

1. Fetch
2. Destroy
3. Create
4. Execute

6) Which of the following is a behavior RTL description to enable the exception

1. IE ← 0
2. IE ←1
3. IE ← 8
4. IE ← -1

7) In a non-pipelined machine, there would be on instruction processed after an average of ____ cycle.

1. 3
2. 4
3. 2
4. 5

8) Among the two approaches available to design a control unit, hardwired approach is relatively _____ as compared to micro-programming.

1. Average
2. Slow
3. Better
4. Faster

9) Below given RTL description belongs to which stage of pipe-lining

IR2←M[PC];

PC2←PC+4;

1. Instruction fetches
2. ALU operation
3. Memory access
4. Instruction decodes

10) A __________ processor is based on a very long instruction word.

1. VLIW
2. SRC
3. FALCON-A
4. FALCON-E